Staff/ Sr Staff/Principal Engineer, STA
Renesas Electronics · Bengaluru, KA, India
About the role
Staff/Sr Staff/Principal Engineer for Static Timing Analysis (STA) and Logic Synthesis. Owns RTL-to-gate conversion, constraint development, and timing closure for high-performance chips.
What you'll do
- Own and execute hierarchical synthesis flows from SystemVerilog RTL to gate-level netlists.
- Perform block-level and full-chip STA across multi-mode multi-corner scenarios.
- Architect, validate, and manage constraints (SDC/UPF).
- Implement and verify UPF-based low-power architectures.
- Script in Tcl, Python, or Perl to automate flows.
- Mentor junior engineers.
What they're looking for
- 8-13 years of experience in synthesis and STA closure.
- Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related.
- Extensive experience in STA closure on complex designs.
- Experience with synthesis of high-frequency designs.
- Knowledge of EDA tools such as Fusion Compiler, Innovus, Primetime, Tempus, VCLP, LEC.
- Strong scripting skills in Tcl, Python, or Perl.
Key details
- Company
- Renesas Electronics
- Location
- Bengaluru, KA, India
- Work mode
- On-site
- Seniority
- Lead / Principal / Group
- Role category
- Engineering
- Experience
- about 8-13 years in synthesis and STA closure
- Posted
- 17 Oct 2026
- Source
- jobs.smartrecruiters.com