Staff Digital Verification Engineer
Renesas Electronics · Bengaluru, KA, India
About the role
Staff Digital Design Verification Engineer for complex power management SoCs. Owns verification of digital blocks from planning to coverage closure using UVM/SystemVerilog. Collaborates with architecture, design, firmware, and systems teams.
What you'll do
- Own verification of complex digital blocks or major SoC features from requirements to coverage closure.
- Develop feature-based verification plans and identify gaps and corner cases.
- Build and extend reusable SystemVerilog/UVM environments with sequences, scoreboards, checkers, assertions, and coverage.
- Develop constrained random and targeted tests for normal and error scenarios.
- Drive functional, code, toggle, FSM, and assertion coverage closure.
- Debug RTL, testbench, and regression failures; automate workflows.
What they're looking for
- Bachelor's or master's in electrical engineering, computer engineering, computer science, or related.
- 7+ years of digital design verification experience.
- Proficiency in SystemVerilog, UVM, constrained random verification, functional coverage, and SystemVerilog Assertions.
- Experience with RTL and testbench debug.
- Knowledge of digital design fundamentals (state machines, clocks, resets, interrupts, memories, clock-domain crossings).
- Proficiency in Linux and scripting (Python, Bash, Perl, or Tcl).
Key details
- Company
- Renesas Electronics
- Location
- Bengaluru, KA, India
- Work mode
- On-site
- Seniority
- Mid-level
- Role category
- Engineering
- Experience
- 7 or more years of relevant digital design verification experience
- Posted
- 17 Oct 2026
- Source
- jobs.smartrecruiters.com