Staff/ Sr Staff/Principal Engineer, STA
Renesas Electronics · Bengaluru, KA, India
About the role
Backend design expert owning RTL-to-gate synthesis, constraint development and full-chip STA closure for complex chips. Focus on PPA optimization, low-power UPF implementation and timing signoff across multi-mode multi-corner scenarios.
What you'll do
- Own physical-aware hierarchical synthesis flows from SystemVerilog RTL to gate netlists
- Perform block and full-chip STA across MMMC scenarios and drive timing closure
- Architect and validate SDC/UPF constraints for functional and DFT modes
- Implement and verify UPF-based low-power, multi-voltage architectures
- Automate flows and methodologies with Tcl, Python or Perl
What they're looking for
- 8-15 years in synthesis and STA closure
- BE/MS in Electrical or Computer Engineering
- STA closure on complex designs, clock structure understanding
- EDA tools: Fusion Compiler, Innovus, Primetime, Tempus, VCLP, LEC
- Strong scripting in Tcl, Python or Perl
- Power and signal integrity analysis understanding
Key details
- Company
- Renesas Electronics
- Location
- Bengaluru, KA, India
- Work mode
- On-site
- Seniority
- Lead / Principal / Group
- Employment type
- Full-time
- Role category
- Engineering
- Experience
- 8-15 years
- Posted
- 30 Oct 2026
- Source
- jobs.smartrecruiters.com