Sr Staff Verification Engineer
Renesas Electronics · Bengaluru, KA, India
About the role
Senior verification engineer developing SystemVerilog/UVM testbenches for complex integrated circuits. Defines verification plans, achieves coverage closure before tape-out, and participates in silicon debugging.
What you'll do
- Develop chip/module level verification testbench components in SystemVerilog
- Build extendable UVM-based environments using OOP concepts
- Define and execute verification plans with architects and designers
- Achieve coverage completeness via code/functional coverage and assertions
- Debug regression failures and participate in silicon debugging
What they're looking for
- BE/MS in Electronics or Electrical Engineering
- 11-15 years in design/verification of complex projects
- Strong SystemVerilog and UVM verification skills
- Coverage, assertions and cover group expertise
- Debug and regression experience
Key details
- Company
- Renesas Electronics
- Location
- Bengaluru, KA, India
- Work mode
- On-site
- Seniority
- Senior
- Employment type
- Full-time
- Role category
- Engineering
- Experience
- 11-15 years
- Posted
- 30 Oct 2026
- Source
- jobs.smartrecruiters.com